Pure digital and digital-mixed-signal design verification
Simulation based verification using UVM methodology
GLS simulations
Formal Verification
Coverage Analysis
Regression run analysis
Top-level verification in UVM and C
Design specification, micro-architecture documents development
Pre-synthesis setup
RTL code developing/reuse and maintenance
RTL Coverage analysis
Post-synthesis tools setup and run on module level
Full top-level verification in both UVM and direct methodologies
Analog modeling
Analog IP verification
Regression runs
12 years of proven ASIC verification experience
8 years of ASIC Verification using UVM methodology and FPGA Emulation
Highly skilled Digital Design Engineer with 10 years of professional experience and a comprehensive skill set spanning
the entire process from initial concept to full implementation including Power
Aware Design, CDC Analysis, Synthesis, P&R and Verification.
Experienced Digital Design Engineer with extensive expertise covering the
entire development flow, from initial concept to full implementation, including
Power-Aware Design, CDC Analysis, Synthesis, and P&R.
Experience in Verification of Analog Mixed signal ICs. Work on models debugging and closely work with conceptual engineers
Impressed by the expertise in RTL synthesis and UVM methodology. Excellent results.