ASIC verification and Digital Design expertise in cutting-edge technology using UVM methodology and state of the art tools
Pure digital and digital-mixed-signal design verification Simulation based verification using UVM methodology GLS simulations Formal Verification Coverage Analysis Regression run analysis Top-level verification in UVM and C
Design specification, micro-architecture documents development Pre-synthesis setup RTL code developing/reuse and maintenance RTL Coverage analysis Post-synthesis tools setup and run on module level
Full top-level verification in both UVM and direct methodologies Analog modeling Analog IP verification Regression runs
Highly experienced Verification engineer with proven experience achieved on multiple projects for largest semiconductor companies. Expertise in SoC level Verification and assertion based verification with extensive expertise in Formal Verification.
Experienced and highly motivated Senior Design Verification Engineer with over 9 years of experience in the semiconductors industry. Proficient in functional verification, UVM, SystemVerilog, and assertion-based verification. Strong background in embedded systems and firmware development. An adept communicator and team player, committed to delivering high-quality results and dedicated to ongoing learning.
Digital Design Verification Engineer with experience in emulation. Experience gained on various project for multiple clients using SystemVerilog and UVM methodology. Work in challenging environment with cutting edge technology is my main drive
Digital Design Verification Engineer with 8 years of ex- perience gained through multiple project for variety of US, European and Israel clients. Experienced in Block level and SoC verification, covering complete verification path from initial Verification plan development, de- sign reviews, testbench and environment development, testcase coding up to coverage analysis
Highly skilled Digital Design Engineer with a comprehensive skill set spanning the entire process from initial concept to full implementation including Power Aware Design, CDC Analysis, Synthesis, P&R and Verification. Extensive hands-on experience in ASIC design, SoC de- sign and integration. Deep understanding of AMBA(AXI, APB, AXI) protocols, SPI, I2C, DDR. Solid understanding of USB, PCIe. UPF/CPF on several projects. Demonstrated effectiveness in team collaboration, design leadership, initiatives and mentoring junior engineers.
Experienced Digital Design Engineer with extensive exper- tise covering the entire development flow, from initial con- cept to full implementation, including Power-Aware Design, CDC Analysis, Synthesis, and P&R. Comprehensive applied experience in ASIC design, SoC de- sign and integration. Deep understanding of AMBA(AXI, APB, AXI) protocols, SPI, I2C, SVI3. Solid understanding of Ethernet. UPF/CPF on one project. Proven success in collaboration, design leadership, and mentoring junior engineers.